Chiplet Architect responsible for defining the architecture of next‑generation multi‑die and chiplet‑based systems. The role spans system partitioning, interconnect and coherency design, workload distribution, and electrical/packaging requirements, while also driving industry standardization, validation methodologies, and chip‑to‑chip protocol analysis in close collaboration with silicon, packaging, software, and ecosystem partners.
Step into the future of innovation by joining imec’s Research Center in Heilbronn at the heart of the rapidly evolving Innovation Park Artificial Intelligence (IPAI).
About imec Germany
Imec Heilbronn is a new regional hub pioneering open chiplet architectures that will power the next generation of automotive innovation and AI‑driven systems. Situated at the heart of the Innovation Park Artificial Intelligence (IPAI), imec Germany brings together world‑class semiconductor expertise and a vibrant ecosystem of AI innovation. This unique combination positions the site as a catalyst for technological breakthroughs that will shape the next generation of mobility and intelligent systems.
The Advanced Chip Design Accelerator (ACDA) is the core of our mission in Heilbronn—establishing a state‑of‑the‑art competence center dedicated to advanced chiplet design, system integration, and cutting‑edge methodologies. ACDA provides the expertise and tools needed to bridge the gap between early‑stage research and industrial adoption, enabling faster, safer, and more scalable deployment of chiplet‑based technologies in the automotive domain. Building on the foundation of imec’s Automotive Chiplet Program (ACP), ACDA extends this work into a regional accelerator that translates imec’s research leadership into practical, industry‑ready solutions. By combining advanced design capabilities with deep local collaboration, ACDA empowers both regional and global automotive players to derisk development, accelerate innovation cycles, and industrialize next‑generation chiplet platforms with confidence.
Be part of the team from the very beginning, joining us as a Chiplet Architect!
What you will do
As a Chiplet Architect, you will be a key contributor to our growing multidisciplinary team, shaping the next generation of scalable, high‑performance multi‑die systems. Your work will span architecture definition, standardization, and system‑level enablement across silicon, packaging, and software domains. In this role, you will:
- Architect multi‑die systems and chiplet‑based platforms, defining system partitioning strategies across compute, memory, I/O, and accelerator dies to optimize performance, power, cost, and scalability.
- Define and influence new industry standards for chiplet‑based and multi‑die systems, contributing to ecosystem‑wide specifications for interoperability, scalability, testing, and long‑term reuse.
- Develop workload distribution strategies across multiple dies, considering latency, bandwidth, power efficiency, coherency, and reliability constraints in heterogeneous systems.
- Specify architectural properties for next‑generation multi‑die systems, including interconnect topology, coherency models, clocking, power management, security, and fault tolerance.
- Define electrical and signalling requirements for advanced packaging, including design rules for high‑speed die‑to‑die links, signal integrity, power integrity, and thermal considerations in 2.5D and 3D integration schemes.
- Drive the development of chiplet validation, characterization, and testing methodologies, including pre‑ and post‑package testing, system‑level bring‑up strategies, and silicon–package co‑validation.
- Contribute to the development of compliance and interoperability standards for chip‑to‑chip communication in advanced packages, ensuring robust operation across vendors, processes, and packaging technologies.
- Perform protocol analysis of chip‑to‑chip communication, evaluating existing and emerging die‑to‑die protocols with respect to performance, power, latency, reliability, and scalability, and identifying gaps and improvement opportunities.
- Collaborate closely with cross‑functional teams including silicon design, packaging, software, system architecture, and external partners to align architectural decisions with product and ecosystem requirements.
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its local footprint in Heilbronn, Germany. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
Who you are
Required skills
- MSc or Phd in Electrical Engineering, Computer Engineering, Embedded Systems, or a closely related field
- Strong understanding of computer architecture, SoC design principles, and system‑level trade-offs (performance, power, area, cost, scalability)
- Solid knowledge of chiplet‑based and multi‑die architectures, including die partitioning, interconnect topologies, and heterogeneous integration
- Experience with or strong understanding of chip‑to‑chip / die‑to‑die communication, including protocol concepts, latency/bandwidth trade‑offs, and reliability considerations
- Familiarity with advanced packaging technologies (e.g., 2.5D, 3D integration), including electrical, signal‑integrity, power‑integrity, and thermal aspects
- Excellent problem‑solving and analytical skills, with the ability to debug complex system‑level issues across hardware boundaries
- A broad technical curiosity and willingness to embrace new challenges across disciplines, from architecture and packaging to validation and standardization
- Experience with or exposure to industry standardization efforts (e.g., interconnects, packaging, or chiplet ecosystems)
- Knowledge of automotive system design, functional safety, reliability, or long‑lived product requirements
- Experience with system‑level validation, testing, or compliance methodologies for complex hardware systems
- Strong communication skills in English and German, with the ability to clearly convey complex technical concepts to diverse audiences
